The present invention is related to the automatic testing of electrical materials, components and circuits and, in particular, to an architecture for a test system.
Automatic testing of electrical materials, components and circuits has become pervasive. In many cases, every device is tested and, in general, many more are tested than in the past and more types of tests are made. In order to more efficiently make measurements on a device under test (DUT), performing multiple tests simultaneously (i.e., in parallel) has become desirable.
There are typically a number of procedures to be executed. These procedures may be dynamic. Some procedures may require some others to be finished first, or cooperate together to complete an action in maximum efficiency, or conflict with some others. Therefore, they should not run immediately when they get into the processor. They may need to wait until sufficient procedures are known, and then get executed in proper combinations and sequence.
This may require that a procedure be held and then run in the future. In addition, resource conflicts should be avoided and result integrity needs to be maintained.
Traditional parametric tests are sequential tests, which connect and measure one device at one time. Parallel tests allows multiple instruments to connect with multiple devices, force signals and measure responses of the devices at the same time, or, in parallel. This technique is extremely useful when throughput of a production line is critical. However, since these devices may be interconnected, they may interact with each other. Therefore, some test procedures should avoid running in parallel with interacting ones. On the other hand, some tests prefer to run in parallel with those dealing with isolated devices. Since different products have different device interconnections, the best combinations of the devices are numerous.
This brings a fundamental problem: How to program the parallel test functions for these various combinations? The brute force method would be writing functions for all possibilities: one resistor in parallel with one transistor, two resistors and one transistor, one resistor and two transistors, four transistors, eight resistors, etc. However, the number of combinations is huge. If there are tens (which is typical) of individual parameter test algorithms, it is essentially impossible to cover all possible cases.